`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   19:54:28 06/21/2015
// Design Name:   StoreControlUnit
// Module Name:   D:/Libraries/Documents/Ingenieria en Comp/MIPS/trunk/Final-Mips/StoreCUTest.v
// Project Name:  Final-Mips
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: StoreControlUnit
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module StoreCUTest;

	// Inputs
	reg [31:0] in;
	reg [1:0] ctrl;

	// Outputs
	wire [31:0] out;

	// Instantiate the Unit Under Test (UUT)
	StoreControlUnit uut (
		.in(in), 
		.out(out), 
		.ctrl(ctrl)
	);

	initial begin
		// Initialize Inputs
		in = 32'h 76543210;
		ctrl = 0;

		// Wait 100 ns for global reset to finish
		#100;
		// Add stimulus here
		#100;
		ctrl = 2'b 01;
		#100;
		ctrl = 2'b 11;
		#100;
		ctrl = 2'b 00;
		

	end
      
endmodule

